搜索资源列表
Altera_IP_verilog
- Altera IP的产生与实现。定制一个8B10B编码器，采用verilog语言建立仿真模型，并验证。-Altera IP generation and implementation. Customize a 8B10B encoder, using verilog language, a simulation model, and verify.
rsencoder_latest.tar
- reed solomon encoder in verilog-reed solomon encoder in verilog
adder1
- 此源代码是基于Verilog语言的“与-或-非”门电路 、用 case语句描述的 4 选 1 数据选择器、同步置数、同步清零的计数器 、用 always 过程语句描述的简单算术逻辑单元、用 begin-end 串行块产生信号波形 ，有广泛的应用，比如编码器领域。-This source code is based on the Verilog language, " and- or- not" gate, with the case statement described in
adder3
- 此源代码是基于Verilog语言的七人投票表决器 、2 个 8 位数相乘 、8 位二进制数的乘法 、同一循环的不同实现方式、使用了`include 语句的 16 位加法器 、条件编译、加法计数器中的进程、任务、测试、函数、用函数和 case语句描述的编码器、阶乘运算函数、测试程序 、顺序执行、并行执行，特别是七人投票表决器，这是我目前发现的最优的用硬件描述的源代码。-The Verilog language source code is based on the seven-vote, and
74hc138
- 用Verilog实现编码器74hc138的功能-Verilog realization of the encoder with the features 74hc138
RS_coder
- 基于verilog的RS编码器 绝对实用-Based on the RS encoder verilog absolute utility
ff_mul
- 基于rs编码器的verilog伽罗华域乘法器设计-Rs encoder based on Galois field multiplier verilog
jjm
- 用Verilog实现的crc16编码器，可以实现任意长度帧的发送信息的crc无失真编码-Implemented with Verilog crc16 encoder can send frames of any length lossless coding of information crc
ASKencoderanddecoder
- ASK编码器与译码器，使用Verilog编写-ASK encoder and decoder, the use of writing Verilog
convert-.m-to-mdl-file
- priority encoder using verilog size is 20kb
Hamming
- 汉明码转换，在FPGA上用verilog实现-hamming encoder, using FPGA
JPEG_Encode_verilog
- JPEG Encoder，JEPEG编码的Verilog代码-JPEG Encoder, JEPEG coded Verilog code
RScoder
- 基于FPGA的RS编码器设计，verilog hdl语言。-RS encoder FPGA-based design, verilog hdl language.
reed_solomon_codec_generator.tar
- reed solomon encoder verilog code.-reed solomon encoder verilog code.
Coder
- 码盘判别方向及计数 用Verilog语言编写-Determine the direction of the encoder and counting with the Verilog language
Hamming_Encoder
- (7,4)Hammming码编码器，verilog代码实现。生成矩阵为G=[1,0,0,0 0,1,0,0 0,0,1,0 0,0,0,1 1,1,1,0 0,1,1,1 1,1,0,1]-(7,4) Hammming Encoder, verilog code. Generator matrix is G = [1,0,0,0 0,1,0,0 0,0,1,0 0,0,0,1 1,1,1,0 0,1, 1,1 1,1,0,1]
Verilog_Encoder
- the encoder operation can perform in verilog to use the case statement.
encode
- FPGA060 verilog 编码器实验及文档-the Verilog FPGA060 experiments and documentation of the encoder
encoder_using_if.v
- this is a verilog code of encoder using if statement.
pri_encoder_using_if.v
- this is a verilog source code for priority encoder using if statement.